View SDA9205_3027508.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the sda 9205-2 is a single monolithic ic containing three separate 8-bit analog to digital converters for video (yuv) applications. it utilizes an advanced vlsi 1.2 m m cmos process providing 30-mhz sampling rates at 8 bits. different digital output multiplex formats are selectable on chip via several control inputs, compatible to inputs of all siemens featureboxes, siemens tv-sam, and ccir 656 output format. the adcs have no missing codes over the full operating temperature range of 0 to + 70 c. operation is from + 5 v dc-power supply. type ordering code package sda 9205-2 q67100-h5069 p-lcc-68-1 (smd) triple 8-bit analog-to-digital-converter preliminary data cmos ic sda 9205-2 p-lcc-68-1 features l three equivalent cmos a/d converters on chip l 30-mhz sample rate l 8-bit resolution l no external sample & hold required l on-chip input buffer for each analog channel l internal clamping circuits for each of the adcs l different digital output multiplex formats: C 3 independent unmultiplexed 8-bit outputs C multiplexed formats compatible to inputs of all siemens featureboxes and siemens tv-sam C ccir 656 output format l overflow and underflow outputs semiconductor group 1 01.94
sda 9205-2 semiconductor group 2 pin configuration (top view)
sda 9205-2 semiconductor group 3 pin definitions and functions pin no. symbol function 63 to 2 c7 to c0 digital outputs of adc c (port c) c0 least significant bit 3 v qgndc output stages supply ground of port c 4 uflc underflow data output of adc c 5 oflc overflow data output of adc c 6 oenc output enable of port c 7 dtc binary/twos complement output port c 8/9/11/17 cont3- cont0 control inputs for different digital output multiplex formats C refer to logic table 10 v refhc reference voltage high of adc c (+ 2.5 v) 12 v ccc analog positive supply voltage of adc c (+5 v) 13 v agndc analog ground of adc c 14 v reflc reference voltage low of adc c (+ 5 v) 15 ainc analog voltage input of adc c 16 v refhb reference voltage high of adc b (+ 2.5 v) 18 v ccb analog positive supply voltage of adc b (+ 5 v) 19 v agndb analog ground of adc b 20 v reflb reference voltage low of adc b (+ 0.5 v) 21 ainb analog voltage input of adc b 22 v refha reference voltage high of adc a (+ 2.5 v) 23 v cca analog positive supply voltage of adc a (+ 5 v) 24 v agnda analog ground of adc a 25 aina analog voltage input of adc a 26 v refla reference voltage low of adc a (+ 0.5 v) 27/29 test factory use only, connect to 0 v 28 dta binary/twos complement output of port a 30 clamp clamp input for all three channels 31 ufla underflow data output of adc a 32 ofla overflow data output of adc a 33 v qgnda output stages supply ground of port a 34 to 41 a7 to a0 digital outputs of adc a (port a) a0 least significant bit 42 oena output enable of port a 43 v ddqa output stages supply voltage of port a
sda 9205-2 semiconductor group 4 44 oenb output enable of port b 45 uflb underflow data output of adc b 46 oflb overflow data output of adc b 47 v qgndb output stages supply ground of port b 48 to 55 b7 to b0 digital outputs of adc b (port b) b0 least significant bit 56 v ddqb output stages supply voltage of port b 57 clk clock input 58 v dgnd digital ground 59 fsy format sync input 60 dtb binary/twos complement output of port b 61 v dd digital positive supply voltage (+ 5 v) 62 v ddqc output stages supply voltage of port c pin definitions and functions (contd) pin no. symbol function
sda 9205-2 semiconductor group 5 circuit description analog to digital converter the sda 9205-2 implements 3 independent 8-bit analog-to-digital converters. they are two step converters with a coarse comparator block and two fine comparator blocks each using pipeline architecture for high speed sampling performance. during the first clock cycle, the coarse comparator samples and determines 4 msbs and one of the fine comparator blocks samples the input voltage. during the second clock cycle this fine comparator block makes its decision for the 4 lsbs. so the coarse comparator block makes its decisions at each clock cycle, the fine comparator blocks make the comparison alternating every two clock cycles. the converter uses the redundancy principle to correct fine conversion. the sample and hold function has been distributed in each comparator due to the two step conversion principle. clamping an internal clamping circuit is provided in each of three analog channels. the analog pins aina, ainb, ainc are switched simultaneously to on chip generated clamping levels by an active high pulse on pin 30 (clamp). clamping levels analog channel dual code components aina 00010000 (y) ainb, ainc 10000000 (u, v)
sda 9205-2 semiconductor group 6 the external clamping capacitance is loaded by on chip current sources (typ. 200 m a) during clamping. so the loading time depends on the values of c ext cl . the loading time for a complete loading cycle is 1200 clk pulses typical (44 m s with 27 mhz clk and c ext cl = 10 nf) as shown in figure 1 . c ext cl = 10 nf, r s = 50 w figure 1 typical clamp timing diagram
sda 9205-2 semiconductor group 7 digital signal processing the digital signal processing block performs averaging of sampled data. the a , b , g 8-bit busses represent the results of dsp function with input data from a, b, c, 8-bit busses. a special dsp function in combination with a special output coding format is defined by four control pins cont0 cont3 (see output coding). figure 2 interfaces of adc-, dsp- and output coding block
sda 9205-2 semiconductor group 8 the following dsp functions are available averaged results are rounded to eight bits (x 0.5 ? 0; x > 0.5 ? 1) a group delay of 0.5 clk cycles exists between dsp (1.0, 2.0) and the other dsp functions. (1.0) a n = a n C 3 adc a (1.1) a n = 1/2 (a n C 4 + a n C 3 ) n = sampling point (2.0) b n = b n C 3 adc b (2.1) b n = 1/2 (b n C 4 + b n C 3 ) (2.2) b 4n = 1/4 (b 4n C 5 + b 4n C 4 + b 4n C 3 + b 4n C 2n ), b 4n C 3,2,1 arbitrarily (2.3) b 8n = 1/8 (b 8n C 7 + b 8n C 6 + ..... + b 8n ), b 8n C 7,6,5,4,3,2,1 arbitrarily (2.0) g n = c n C 3 adc c (2.1) g n = 1/2 (c n C 4 + c n C 3 ) (2.2) g 4n = 1/4 (c 4n C 5 + c 4n C 4 + c 4n C 3 + c 4n C 2 ) g 4n C 3,2,1 arbitrarily (2.3) g 8n = 1/8 (c 8n C 7 + c 8n C 6 + ..... + c 8n ) g 8n C 7,6,5,4,3,2,1 arbitrarily
sda 9205-2 semiconductor group 9 figure 3 dsp function detailed function of dsp block is shown in figure 3 .
sda 9205-2 semiconductor group 10 output coding eight different digital output multiplex formats are available. they are selectable via four control lines cont0 cont3. these multiplexed formats perform combinations of dsp functions of the several converters (a, b, c). dsp functions C output coding combinations format dsp cont3 cont2 cont1 cont0 8:8:8 8:4:4 8:2:2 8:1:1 4:8:8 4:4:4 4:2:2 4:1:1 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.2 1.0 + 2.0 1.1 + 2.3 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.2 1.0 + 2.0 1.1 + 2.3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
sda 9205-2 semiconductor group 11 the digital output data are synchronized by the fsy signal. the first high of fsy defines the first output format byte and is synchronized to clk. in case of asynchronism the first (in formats 8:1:1, 4:1:1 the first and the second) output format byte after fsy had gone high does not contain valid data. timing of fsy, clk and output data is shown in figure 4 with output format 4:1:1. figure 4
sda 9205-2 semiconductor group 12 format 8:8:8 port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b c c7 c6 c5 c4 c3 c2 c1 c0 g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 0000 1.1 + 2.1 0001 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7
sda 9205-2 semiconductor group 13 format 8:4:4 * t tristate port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b b b b b b b g g g g g g g g b b b b b b b b g g g g g g g g b b b b b b b b g g g g g g g g b b b b b b b b g g g g g g g g c c7 c6 c5 c4 c3 c2 c1 c0 t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t* time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 0010 1.1 + 2.1 0011 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6
sda 9205-2 semiconductor group 14 format 8:2:2 * t tristate port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t c c7 c6 c5 c4 c3 c2 c1 c0 t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t* time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 0100 1.1 + 2.2 0101 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 0 6 0 7 0 6 0 5 0 4 0 5 0 4 0 3 0 2 0 3 0 2 0 1 0 0 0 1 0 0 0 7 4 6 4 7 4 6 4 5 4 4 4 5 4 4 4 3 4 2 4 3 4 2 4 1 4 0 4 1 4 0 4
sda 9205-2 semiconductor group 15 format 8:1:1 * t tristate port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t c c7 c6 c5 c4 c3 c2 c1 c0 t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t* time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 0110 1.1 + 2.3 0111 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 0 6 0 7 0 6 0 7 0 6 0 7 0 6 0 5 0 4 0 5 0 4 0 5 0 4 0 5 0 4 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
sda 9205-2 semiconductor group 16 format 4:8:8 port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b c c7 c6 c5 c4 c3 c2 c1 c0 g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 1000 1.1 + 2.1 1001 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7
sda 9205-2 semiconductor group 17 format 4:4:4 port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b c c7 c6 c5 c4 c3 c2 c1 c0 g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 1010 1.1 + 2.1 1011 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6
sda 9205-2 semiconductor group 18 format 4:2:2 port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b b b b b b b b b b b b b b b g g g g g g g g g g g g g g g g b b b b b b b b b b b b b b b b g g g g g g g g g g g g g g g g c c7 c6 c5 c4 c3 c2 c1 c0 b b b b b b b b a a a a a a a a g g g g g g g g a a a a a a a a b b b b b b b b a a a a a a a a g g g g g g g g a a a a a a a a time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 1100 1.1 + 2.2 1101 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6
sda 9205-2 semiconductor group 19 format 4:1:1 * t tristate port bit data a a7 a6 a5 a4 a3 a2 a1 a0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a b b7 b6 b5 b4 b3 b2 b1 b0 b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t b b g g t t t t c c7 c6 c5 c4 c3 c2 c1 c0 t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t* time index n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 dsp function coding cont3 cont2 cont1 cont0 1.0 + 2.0 1110 1.1 + 2.3 1111 dsp bus a 7 0 bit number time index 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 0 6 0 7 0 6 0 7 0 6 0 7 0 6 0 5 0 4 0 5 0 4 0 5 0 4 0 5 0 4 0 3 0 2 0 3 0 2 0 3 0 2 0 3 0 2 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
sda 9205-2 semiconductor group 20 output coding for binary/twos complement mode binary or twos complement output coding is selectable for each separate output port (a, b, c) via control inputs dta, dtb, dtc. this coding is independent from selected formats (8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1). table 1 output coding for formats 8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1 table 1 is valid for v refl = 0.5 v and v refh = 2.5 v v ca = ext. clamping level during clamp high pulse at c ext cl on channel aina. v cb, c = ext. clamping level during clamp high pulse at c ext cl on channel ainb and ainc. in output format 4:2:2 a special suppression of code 0 and code 255 is provided in the binary output mode. step vin converter a vin converter b, c ofl bit ufl bit binary output 7 6 5 4 3 2 1 0 twos complement 7 6 5 4 3 2 1 0 underflow 0 1 . . . . 254 255 overflow < v ca C 0.125 v v ca C 0.125 v v ca C 0.117 v . . . . v ca + 1.867 v v ca + 1.875 v > v ca + 1.875 v < v cb, c C 1 v v cb, c C 1 v v cb, c C 0.992 v . . . . v cb, c + 0.992 v v cb, c + 1 v > v cb, c + 1 v 0 0 0 . . . . . 0 1 1 0 0 . . . . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 . . . . 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
sda 9205-2 semiconductor group 21 table 2 output coding for format 4:2:2 table 2 is valid for v refl = 0.5 v and v refh = 2.5 v v ca = ext. clamping level during clamp high pulse at c ext cl on channel aina. v cb, c = ext. clamping level during clamp high pulse at c ext cl on channel ainb and ainc. step vin converter a vin converter b, c ofl bit ufl bit binary output 7 6 5 4 3 2 1 0 twos complement 7 6 5 4 3 2 1 0 underflow 0 1 2 . . 253 254 255 overflow < v ca C 0.125 v v ca C 0.125 v v ca C 0.117 v . . . . v ca + 1.867 v v ca + 1.875 v > v ca + 1.875 v < v cb, c C 1 v v cb, c C 1 v v cb, c C 0.992 v . . . . v cb, c + 0.992 v v cb, c + 1 v > v cb, c + 1 v 0 0 0 0 . . 0 0 0 1 1 0 0 . . . 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 . . 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0
sda 9205-2 semiconductor group 22 block diagram 1) all voltage values are with respect to network ground terminal absolute maximum ratings parameter symbol limit values unit min. max. supply voltages 1) v cc , v dd 6.5 v input voltage range all inputs v i C 0.3 v cc + 0.3 v ambient temperature t a 070 c storage temperature t stg C 55 125 c
sda 9205-2 semiconductor group 23 characteristics v dd = 5 v 5 %, v cc = 5 v 5 %, v refh = 2.5 v, v refl = 0.5 v, v gnd = 0 v f clk = 27 mhz, all specifications min ( t a ) to max ( t a ) unless otherwise noted parameter symbol limit values unit test condition min. typ. max. power requirements analog supply voltage v cc 4.75 5 5.25 v pins 12, 18, 23 digital supply voltage v dd 4.75 5 5.25 v pin 61 output stage supply voltage v ddq 4.75 5 5.25 v pins 43, 56, 62 analog supply current i cc 160 ma sum of all v cc pins digital supply current i dd 20 ma sum of all v dd pins output stages supply current i ddq 40 ma sum of all v ddq pins supply voltage differential v cc C v dd C 0.25 0.25 v supply voltage differential v ddq C v dd C 0.25 0.25 v reference inputs reference voltage high v refh 2.5 v pins 10, 16, 22 reference voltage low v refl 0.4 0.5 v pins 14, 20, 26 reference current i ref 8 ma pins 10, 16, 22 reference ladder resistance r ref 250 w each analog inputs input range v i 2 vpp single-ended, dc-15 mhz analog input capacitance c i 5 pf aina, ainb, ainc, each required ext clamp capacitance c ext cl 10 nf aina, ainb, ainc, each required signal source resistance r s 200 w analog input current i ain 5 100 na aina, ainb, ainc, each
sda 9205-2 semiconductor group 24 digital inputs l-input voltage h-input voltage v il v ih 0 2.0 0.8 v dd v v input current i i C 10 5 10 m a v i = 0 v, v cc digital outputs l-output voltage h-output voltage v ql v qh 2.4 0.4 v v i sink = 1.6 ma i source = 400 ma high impedance state output current i qz C 20 20 m a v q = 0 v, v cc performance sampling rate 27 30 msps full power bandwidth (C 3 db) bw 10 mhz diff. linearity (d.c.) dnle 0.5 lsb int. linearity (d.c.) inle 0.5 1 lsb clamping level accuracy cla 1 3 lsb gain error ge 3 lsb differential gain 1) dg 3% f i = 3.6/4.4 mhz ain = 1/10 fsr 2 ) differential phase 1) dp 3 degree signal-to-noise ratio 4.4 mhz sinus a s/n 42 46 db without harmonics 4:1:1 mode dsp 1.0 harmonic distorsion 2./4. order 3. order 5./6. order C 40 C 40 C 46 db db db 4.4 mhz fundamental 4.4 mhz fundamental 4.4 mhz fundamental supply voltage rejection 2.5 %fsr/v 2) 1) sample test 2) full scale range (fsr) = 2 v as specified characteristics (contd) v dd = 5 v 5 %, v cc = 5 v 5 %, v refh = 2.5 v, v refl = 0.5 v, v gnd = 0 v f clk = 27 mhz, all specifications min ( t a ) to max ( t a ) unless otherwise noted parameter symbol limit values unit test condition min. typ. max.
sda 9205-2 semiconductor group 25 figure 5 timing diagram port a, b, c timing (see figure 5) output data delay time t qd 25 ns c l = 15 pf output data hold time t qh 6ns c l = 15 pf clk pulse width t wh ; t wl 10 ns c l = 15 pf clk rise time t tlh 5ns c l = 15 pf clk fall time t thl 5ns c l = 15 pf input data setup time t su 7ns c l = 15 pf input data hold time t ih 6ns c l = 15 pf clamp input pulse width t ci 10 clk cycles 1 nf ext. clamp cap. characteristics (contd) v dd = 5 v 5 %, v cc = 5 v 5 %, v refh = 2.5 v, v refl = 0.5 v, v gnd = 0 v f clk = 27 mhz, all specifications min ( t a ) to max ( t a ) unless otherwise noted parameter symbol limit values unit test condition min. typ. max.
sda 9205-2 semiconductor group 26 sample output data-delay is shown on format 8:8:8 with dsp function 1.0 + 2.0 figure 6 diagram of complete timing there is a delay of 9 clock cycles between sampling of an analog input signal and the corresponding digital output signal.
sda 9205-2 semiconductor group 27 figure 8 blocking the sda 9205-2 capacitors: 100 nf - ceramic 10 nf - tantal 47 m f - elko figure 7 typ. snr (without harmonics) versus analog frequency (411 mode dsp 1.0) references
sda 9205-2 semiconductor group 28 figure 8 (contd) blocking the sda 9205-2 v cc v dd grounding
sda 9205-2 semiconductor group 29 figure 8 (contd) blocking the sda 9205-2 chip capacitors 100 nf (as near as possible to the socket)
sda 9205-2 semiconductor group 30 figure 9 application circuit 1 (4:1:1 format, for siemens featurebox)
sda 9205-2 semiconductor group 31 figure 10 application circuit 2 (4:1:1 format, for general application)

▲Up To Search▲

Price & Availability of SDA9205

	To Download SDA9205 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .